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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 1/17 preliminar y m5m5v5636gpi rev.0.1 description the m5m5v5636gp is a family of 18m bit synchronous srams organized as 524288-words by 36-bit. it is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. mitsubishi's srams are fabricated with high performance, low power cmos technology, providing greater reliability. m5m5v5636gp operates on 3.3v power/ 2.5v i/o supply or a single 3.3v power supply and are 3.3v cmos compatible. features ? supported industrial temperature range ? fully registered inputs and outputs for pipelined operation ? fast clock speed: 167 mhz and 133mhz ? fast access time: 3.8 ns and 4.2ns ? single 3.3v -5% and +5% power supply v dd ? separate v ddq for 3.3v or 2.5v i/o ? individual byte write (bwa# - bwd#) controls may be tied low ? single read/write control pin (w#) ? cke# pin to enable clock and suspend operations ? internally self-timed, registers outputs eliminate the need to control g# ? snooze mode (zz) for power down ? linear or interleaved burst modes ? three chip enables for simple depth expansion package 100pin tqfp application high-end networking products that require high bandwidth, such as switches and routers . function synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. synchronous signals include : all addresses, all data inputs, all chip enables (e1#, e2, e3#), address advance/load (adv), clock enable (cke#), byte write enables (bwa#, bwb#, bwc#, bwd#) and read/write (w#). write operations are controlled by the four byte write enables (bwa# - bwd#) and read/write(w#) inputs. all writes are conducted with on-chip synchronous self-timed write circuitry. asynchronous inputs include output enable (g#), clock (clk) and snooze enable (zz). the high input of zz pin puts the sram in the power-down state.the linear burst order (lbo#) is dc operated pin. lbo# pin will allow the choice of either an interleaved burst, or a linear burst. all read, write and deselect cycles are initiated by the adv low input. subsequent burst address can be internally generated as controlled by the adv high input. part name table part name access cycle active current (max.) standby current (max.) m5m5v5636gp ? 16i 3.8ns 6.0ns 380ma 30ma m5m5v5636gp ? 13i 4.2ns 7.5ns 350ma 30ma january 31, 2003 rev.0.1 preliminary notice: this is not final specification. some parametric limits are subject to change.
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 2/17 preliminar y m5m5v5636gpi rev.0.1 pin configuration(top view) 100pin tqfp note1. mch means "must connect high". mch should be connected to high. dqpb dqb dqb vddq vssq dqb dqb dqb dqb vssq vddq dqb dqb vss mch vdd zz dqa dqa vddq vssq dqa dqa dqa dqa vssq vddq dqa dqa dqpa 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqp c dq c dq c vddq vssq dq c dq c dq c dq c vssq vddq dq c dq c mch vdd mch vss dqd dqd vddq vssq dqd dqd dqd dqd vssq vddq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a9 a8 a17 a18 ad v g # cke # w # cl k vss vdd e3 # bwa # bwb # bwc # bwd # e2 e1 # a7 a6 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 a10 a11 a12 a13 a14 a15 a16 nc nc vdd vss nc nc a0 a1 a2 a3 a4 a5 lbo# 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 m5m5v5636gp
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 3/17 preliminar y m5m5v5636gpi rev.0.1 block diagram note2. the block diagram does not include the boundary scan logic. note3. the block diagram illustrates simplified device operation. see truth table, pin function and timing diagrams for detailed information. address register 19 write address register1 write address register2 a1 a0 linear/ interleaved burst counter d1 d0 q1 q0 a1' a0' 19 17 write registry and data coherency control logic byte1 write drivers byte2 write drivers byte3 write drivers byte4 write drivers 256kx36 memory array output registers output select output buffers input register1 input register0 read logic 19 19 36 dqa lbo# dqpa dqb dqpb dqc dqpc dqd dqpd a0 a1 a2 ~ 18 clk cke# zz e2 e1# e3# g# bwa# bwb# bwc# bwd# adv w# v dd v ddq v ss
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 4/17 preliminar y m5m5v5636gpi rev.0.1 pin function pin name function a0~a18 synchronous address inputs these inputs are registered and must meet the setup and hold times around the rising edge of clk. a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bwa#, bwb#, bwc#, bwd# synchronous byte write enables these active low inputs allow individual bytes to be written when a write cycle is active and must meet the setup and hold times around the rising edge of clk. byte writes need to be asserted on the same cycle as the address. bws are associated with addresses and apply to subsequent data. bwa# controls dqa, dqpa pins; bwb# controls dqb, dqpb pins; bwc# controls dqc, dqpc pins; bwd# controls dqd, dqpd pins. clk clock input this signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock's rising edge. e1# synchronous chip enable this active low input is used to enable the device and is sampled only when a new external address is loaded (adv is low). e2 synchronous chip enable this active high input is used to enable the device and is sampled only when a new external address is loaded (adv is low). this input can be used for memory depth expansion. e3# synchronous chip enable this active low input is used to enable the device and is sampled only when a new external address is loaded (adv is low). this input can be used for memory depth expansion. g# output enable this active low asynchronous input enable the data i/o output drivers. adv synchronous address advance/load when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when high, w# is ignored. a low on this pin permits a new address to be loaded at clk rising edge. cke# synchronous clock enable this active low input permits clk to propagate throughout the device. when high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet setup and hold times around the rising edge of clk. zz snooze enable this active high asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when active, all other inputs are ignored. when this pin is low or nc, the sram normally operates. w# synchronous read/write this active input determines the cycle type when adv is low. this is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on the pin permits byte write operations and must meet the setup and hold times around the rising edge of clk. full bus width writes occur if all byte write enables are low. dqa,dqpa,dqb,dqpb dqc,dqpc,dqd,dqpd synchronous data i/o byte ?a? is dqa , dqpa pins; byte ?b? is dqb, dqpb pins; byte ?c? is dqc, dqpc pins; byte ?d? is dqd,dqpd pins. input data must meet setup and hold times around clk rising edge. lbo# burst mode control this dc operated pin allows the choice of either an interleaved burst or a linear burst. if this pin is high or nc, an interleaved burst occurs. when this pin is low, a linear burst occurs, and input leak current to this pin. v dd v dd core power supply v ss v ss core ground v ddq v ddq i/o buffer power supply v ssq v ssq i/o buffer ground mch must connect high these pins should be connected to high nc no connect these pins are not internally connected and may be connected to ground.
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 5/17 preliminar y m5m5v5636gpi rev.0.1 dc operated truth table name input status operation high or nc interleaved burst sequence lbo# low linear burst sequence note4. lbo# is dc operated pin. note5. nc means no connection. note6. see burst sequence table about interleaved and linear burst sequence. burst sequence table interleaved burst sequence (when lbo# = high or nc) operation a18~a2 a1,a0 first access, latch external address a18~a2 0 , 0 0 , 1 1 , 0 1 , 1 second access(first burst address) latched a18~a2 0 , 1 0 , 0 1 , 1 1 , 0 third access(second burst address) latched a18~a2 1 , 0 1 , 1 0 , 0 0 , 1 fourth access(third burst address) latched a18~a2 1 , 1 1 , 0 0 , 1 0 , 0 linear burst sequence (when lbo# = low) operation a18~a2 a1,a0 first access, latch external address a18~a2 0 , 0 0 , 1 1 , 0 1 , 1 second access(first burst address) latched a18~a2 0 , 1 1 , 0 1 , 1 0 , 0 third access(second burst address) latched a18~a2 1 , 0 1 , 1 0 , 0 0 , 1 fourth access(third burst address) latched a18~a2 1 , 1 0 , 0 0 , 1 1 , 0 note7. the burst sequence wraps around to its initial state upon completion. truth table e1# e2 e3# zz adv w# bwx# g# cke# clk dq address used operation h x x l l x x x l l->h high-z none deselect cycle x l x l l x x x l l->h high-z none deselect cycle x x h l l x x x l l->h high-z none deselect cycle x x x l h x x x l l->h high-z none continue deselect cycle l h l l l h x l l l->h q external read cycle, begin burst x x x l h x x l l l->h q next read cycle, continue burst l h l l l h x h l l->h high-z external nop/dummy read, begin burst x x x l h x x h l l->h high-z next dummy read, continue burst l h l l l l l x l l->h d external write cycle, begin burst x x x l h x l x l l->h d next write cycle, continue burst l h l l l l h x l l->h high-z none nop/write abort, begin burst x x x l h x h x l l->h high-z next write abort, continue burst x x x l x x x x h l->h - current ignore clock edge, stall x x x h x x x x x x high-z none snooze mode note8. ?h? = input vih; ?l? = input vil; ?x? = input vih or vil. note9. bwx#=h means all synchronous byte write enables (bwa#,bwb#,bwc#,bwd#) are high. bwx#=l means one or more synchronous byte write enables are low. note10. all inputs except g# and zz must meet setup and hold times around the rising edge (low to high) of clk.
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 6/17 preliminar y m5m5v5636gpi rev.0.1 state diagram note11. the notation "x , x , x" controlling the state transitions above indicate the state of inputs e, adv and w# respectivel y. note12. if (e1# = l and e2 = h and e3# = l) then e="t" else e="f". note13. "h" = input vih; "l" = input vil; "x" = input vih or vil; "t" = input "true"; "f" = input "false". read begin burst t , l , h read continue burst write begin burst write continue burst deselect x , h , x x , h , x x , h , x t , l , l t , l , l t , l , h x , h , x t , l , h t , l , l x , h , x f , l , x t , l , h f , l , x f , l , x t , l , l t , l , l t , l , h transition next state current state input command code f key
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 7/17 preliminar y m5m5v5636gpi rev.0.1 write truth table w# bwa# bwb# bwc# bwd# function h x x x x read l l h h h write byte a l h l h h write byte b l h h l h write byte c l h h h l write byte d l l l l l write all bytes l h h h h write abort/nop note14. ?h? = input vih; ?l? = input vil; ?x? = input vih or vil. note15. all inputs except g# and zz must meet setup and hold times around the rising edge (low to high) of clk. absolute maximum ratings symbol parameter conditions ratings unit v dd power supply voltage -1.0*~4.6 v v ddq i/o buffer power supply voltage -1.0*~4.6 v v i input voltage -1.0~v ddq +1.0** v v o output voltage with respect to v ss -1.0~v ddq +1.0** v pd maximum power dissipation (v dd ) 1180 mw t opr operating temperature industrial temperature -40~85 c t stg storage temperature -65~150 c note16.* this is ?1.0v when pulse width 2ns, and ?0.5v in case of dc. ** this is ?1.0v~v ddq +1.0v when pulse width 2ns, and ?0.5v~v ddq +0.5v in case of dc.
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 8/17 preliminar y m5m5v5636gpi rev.0.1 dc electrical characteristics (ta=-40~85c, v dd =3.135~3.465v, unless otherwise noted) limits symbol parameter condition min max unit v dd power supply voltage 3.135 3.465 v v ddq = 3.3v 3.135 3.465 v ddq i/o buffer power supply voltage v ddq = 2.5v 2.375 2.625 v v ddq = 3.135~3.465v 2.0 v ih high-level input voltage v ddq = 2.375~2.625v 1.7 v ddq +0.3* v v ddq = 3.135~3.465v 0.8 v il low-level input voltage v ddq = 2.375~2.625v -0.3* 0.7 v v oh high-level output voltage i oh = -2.0ma v ddq -0.4 v v ol low-level output voltage i ol = 2.0ma 0.4 v input current except zz and lbo# v i = 0v ~ v ddq 10 input current of lbo# v i = 0v ~ v ddq 100 i li input current of zz v i = 0v ~ v ddq 100 a i lo off-state output current v i (g#) v ih , v o = 0v ~ v ddq 10 a 6.0ns cycle(167mhz) 380 i cc1 power supply current : operating device selected; output open v i v il or v i v ih zz v il 7.5ns cycle(133mhz) 350 ma 6.0ns cycle(167mhz) 160 i cc2 power supply current : deselected device deselected v i v il or v i v ih zz v il 7.5ns cycle(167mhz) 130 ma i cc3 cmos standby current (clk stopped standby mode) device deselected; output open v i v ss +0.2v or v i v ddq -0.2v clk frequency=0hz, all inputs static 30 ma i cc4 snooze mode standby current snooze mode zz v ddq -0.2v, lbo# v dd -0.2v 30 ma 6.0ns cycle(167mhz) 130 i cc5 stall current device selected; output open cke# v ih v i v ss +0.2v or v i v ddq -0.2v 7.5ns cycle(133mhz) 120 ma note17.*v ilmin is ?1.0v and v ih max is v ddq +1.0v in case of ac(pulse width 2ns). note18."device deselected" means device is in power-down mode as defined in the truth table.
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 9/17 preliminar y m5m5v5636gpi rev.0.1 capacitance limits symbol parameter conditions min typ max unit c i input capacitance v i =gnd, v i =25mvrms, f=1mhz 6 pf c o input / output(dq) capacitance v o =gnd, v o =25mvrms, f=1mhz 8 pf note19.this parameter is sampled. thermal resistance 4-layer pc board mounted (70 x 70 x 1.6mmt) limits symbol parameter conditions min typ max unit ja thermal resistance junction ambient air velocity=0m/sec 28.18 c/w air velocity=2m/sec 20.33 c/w jc thermal resistance junction to case 6.64 c/w note20.this parameter is sampled. ac electrical characteristics (ta=-40~85c, v dd =3.135~3.465v, unless otherwise noted) (1)measurement condition input pulse levels v ih =v ddq , v il =0v input rise and fall times faster than or equal to 1v/ns input timing reference levels v ih =v il =0.5*v ddq output reference levels v ih =v il =0.5*v ddq output load fig.1 note21.valid delay measurement is made from the v ddq /2 on the input waveform to the v ddq /2 on the output waveform. input waveform should have a slew rate of faster than or equal to 1v/ns. note22.tri-state toff measurement is made from the v ddq /2 on the input waveform to the output waveform moving 20% from its initial to final value v ddq /2. note:the initial value is not v ol or v oh as specified in dc electrical characteristics table. note23. tri-state ton measurement is made from the v ddq /2 on the input waveform to the output waveform moving 20% from its initial value v ddq /2 to its final value. note:the final value is not v ol or v oh as specified in dc electrical characteristics table. note24.clocks,data,address and control signals will be tested with a minimum input slew rate of faster than or equal to 1v/ns. z o =50 ? 50 ? q v t =0.5*v ddq 30pf (including wiring and jig) fi g. 1 o utput l oa d v ddq / 2 v ddq / 2 t plh t phl input waveform output waveform v ddq / 2 input waveform vh-(0.2(vh-vz)) vz+(0.2(vh-vz)) 0.2(vz-vl) vz-(0.2(vz-vl)) toff ton vz (toff) (ton) vh vl output waveform fi g. 2 tdl y measurement fig.3 tri-state measurement
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 10/17 preliminar y m5m5v5636gpi rev.0.1 (2)timing characteristics limits 167mhz 133mhz -16 -13 symbol parameter min max min max unit clock t khkh clock cycle time 6.0 7.5 ns t khkl clock high time 2.7 3.0 ns t klkh clock low time 2.7 3.0 ns output times t khqv clock high to output valid 3.8 4.2 ns t khqx clock high to output invalid 1.5 1.5 ns t khqx1 clock high to output in low-z 1.5 1.5 ns t khqz clock high to output in high-z 1.5 3.8 1.5 4.2 ns t glqv g# to output valid 3.8 4.2 ns t glqx1 g# to output in low-z 0.0 0.0 ns t ghqz g# to output in high-z 3.8 4.2 ns setup times t avkh address valid to clock high 1.5 1.5 ns t ckevkh cke# valid to clock high 1.5 1.5 ns t advvkh adv valid to clock high 1.5 1.5 ns t wvkh write valid to clock high 1.5 1.5 ns t bvkh byte write valid to clock high (bwa#~bwd#) 1.5 1.5 ns t evkh enable valid to clock high (e1#,e2,e3#) 1.5 1.5 ns t dvkh data in valid clock high 1.5 1.5 ns hold times t khax clock high to address don?t care 0.5 0.5 ns t khckex clock high to cke# don?t care 0.5 0.5 ns t khadvx clock high to adv don?t care 0.5 0.5 ns t khwx clock high to write don?t care 0.5 0.5 ns t khbx clock high to byte write don?t care (bwa#~bwb#) 0.5 0.5 ns t khex clock high to enable don?t care (e1#,e2,e3#) 0.5 0.5 ns t khdx clock high to data in don?t care 0.5 0.5 ns zz t zzs zz standby 2*t khkh 2*t khkh ns t zzrec zz recovery 2*t khkh 2*t khkh ns note25.all parameter except t zzs , t zzrec in this table are measured on condition that zz=low fix. note26.test conditions is specified with the output loading shown in fig.1 unless otherwise noted. note27. t khqx1 , t khqz , t glqx1 , t ghqz are sampled. note28.lbo# is static and must not change during normal operation.
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 11/17 preliminar y m5m5v5636gpi rev.0.1 (3)read timing note29.q(an) refers to output from address an. q(an+1) refers to output from the next internal burst address following an. note30. e# represents three signals. when e# is low, it represents e1# is low, e2 is high and e3# is low. note31.zz is fixed low . read a2 a1 a2 a3 q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2) q(a3) q(a3+1) clk cke# e# adv w# bwx# add dq g# read a1 burst read a2+1 stall burst read a2+2 burst read a2+3 burst read a2 deselect continue deselect read a3 burst read a3+1 burst read a3+2 burst read a3+3 t khkh don't care undefined t klkh t khkl t khckex t ckevkh t khex t evkh t khadvx t advvkh t khwx t wvkh t khax t avkh t khqx1 t khqv t khqx t glqv t ghqz t glqx1 t khqz
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 12/17 preliminar y m5m5v5636gpi rev.0.1 (4)write timing note32.q(an) refers to output from address an. q(an+1) refers to output from the next internal burst address following an. note33. e# represents three signals. when e# is low, it represents e1# is low, e2 is high and e3# is low. note34.zz is fixed low. burst write a2+1 write a2 a1 a2 a4 clk cke# e# adv w# bwx# add dq g# write a1 nop burst write a2+3 write a2 write a3 nop burst write a4+1 stall burst write a4+2 burst write a4+3 a3 d(a1) d(a2) d(a2+1) d(a2+3) d(a2) d(a3) d(a4) d(a4+1) don't care undefined t khkh t klkh t khkl t khckex t ckevkh t khex t evkh t khadvx t advvkh t khwx t wvkh t khbx t bvkh t khax t avkh t khdx t dvkh write a4
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 13/17 preliminar y m5m5v5636gpi rev.0.1 (5)read/write timing note35.q(an) refers to output from address an. q(an+1) refers to output from the next internal burst address following an. note36. e# represents three signals. when e# is low, it represents e1# is low, e2 is high and e3# is low. note37.zz is fixed low. write a2 a1 a2 a5 q(a1) q(a3+1) q(a5) clk cke# e# adv w# bwx# add dq g# read a1 read a2 write a3 burst write a3+1 read a3 burst read a3+1 deselect write a4 stall read a5 burst read a5+1 burst read a5+2 a2 a3 a3 a4 d(a2) q(a2) d(a3) d(a3+1) q(a3) d(a4) don't care undefined t khkh t klkh t khkl t khckex t ckevkh t khex t evkh t khadvx t advvkh t khwx t wvkh t khbx t bvkh t khax t avkh t khqx1 t khqv t khqv t khdx t dvkh
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 14/17 preliminar y m5m5v5636gpi rev.0.1 (6)snooze mode timing clk zz all inputs (except zz) q deselect or read only snooze mode t zzs t zzrec
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 15/17 preliminar y m5m5v5636gpi rev.0.1 package outline plastic 100pin 14x20 mm body note38. dimensions *1 and *2 don't include mold flash. note39 dimension *3 doesn't include trim off set. note40.all dimensions in millimeters. 1.6 max 0.65 nom 0.1 *3 0.32+0.06 -0.07 0.13 m a 0.125+0.05 -0.02 (1.4) 0.1250.075 0~7 0.50.15 detail a *2 200.1 220.2 160.2 *1 140.2 80 51 50 31 30 1 100 81
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 16/17 preliminar y m5m5v5636gpi rev.0.1 revision history rev. no. history date 0.0 first revision september 20, 2002 preliminary 0.1 dc electrical characteristics changed ili limit from 10ua to 100ua (input leakage current of zz and lbo#) changed icc3 and icc4 limit from 20ma to 30ma (standby current) january 31, 2003 preliminary
mitsubishi lsis m5m5v5636gp ?16i,13i 18874368-bit(524288-word by 36-bit) network sram 17/17 preliminar y m5m5v5636gpi rev.0.1 keep safety first in your circuit designs! z mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxi liary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials z these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customer?s application; they do not convey any license under any intellectual property rights, or any other rights, belonging t o mitsubishi electric corporation or a third party. z mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party?s rights, originat ing in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. z all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents info rmation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi s emiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com) . z when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and p roducts. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. z mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconduc tor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportati on, vehicular, medical, aerospace, nuclear, or undersea repeater use. z the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. z if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. z please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein.

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